The present invention relates to electronic circuits, and more particularly, to clock distribution techniques for channels.
Many high-speed data transmission protocols can support several channels. For example, the Peripheral Component Interconnect Express 2.0 (PCIE-GEN2) protocol supports 4, 8, or 12 channels, the QuickPath Interconnect (QPI) protocol supports up to 20 channels, the HyperTransport protocol can use up to 16 or 30 channels, and the Interlaken protocol is designed to support from 1 to 24 channels. Interlaken supports a frequency range of 4.9 gigabytes per second (Gbps) to 6.375 Gbps.